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HLS master IC, 3.3 V (5 V–tolerant)

The MKY36 is a center (hearafter "master") IC for the Hi-speed Link System (HLS). If it is connected to a CPU using an 8-bit or 16-bit bus, it can be accessed from the CPU. It contains memory and has an I/O control register (DIN and DOUT areas) for each slave address and communication control registers for functions such as communication startup and error checking.

When the CPU accesses the MKY36, it recognizes the MKY36 as SRAM, so the CPU can control communication and DIO just by reading and writing to the memory of the MKY36. The MKY36 has two receiving pins (RXD1 and RXD2), so it can control two RS-485 communication lines. It also has two interrupt pins, so it can be used for a variety of interrupt functions such as input update interrupt and communication error interrupt. In addition to this wealth of interrupt functions, the MKY36 also contains built-in communication protocol, allowing it to relieve the load on the CPU for communication functions.



Bus width 8 bits / 16 bits
Control terminal CS, RD, WRL, WRH
Interrupt pin 2 pins
CPU voltage 3.3 V (5 V tolerant)
Communication method HLS communication (Full-duplex/Half-duplex)
Transfer rate 3/6/12 Mbps
Package TQFP 64-pin
Package dimension 12×12×1.2 mm(0.5 mm pitch)
Operating ambient temperature -40 to +85℃
Supply voltage 3.3 V
External input operating
48 MHz

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